NANO_C: NanoComputing Project

Application Specific NanoComputing Systems

1. Exploring the Unprecedented Computation Power of Nanoelectronics
2. Achieving High Performance, Robustness, and Scalability
3. Exposing New Forms of Parallelism and New Reliability-Performance Trade- offs
4. Exploiting Novel Uncertainty Management Techniques

General Purpose NanoComputing Systems

Novel Reliability-Aware Performance Enhancing Microarchitectural Techniques

Blue bars show the IPC (Instructions Per Cycle) for a machine enhanced with reliability-aware microarchitectural techniques. Red bars show the IPC for a baseline machine. For each benchmark, six different target nanotechnologies were simulated, each with a different reliability (i.e., susceptibility to soft/transient errors), and thus different delays for fault-tolerant microarchitectural components. The target nanotechnologies for each benchmark are sorted in decreasing reliability order. We observe that reliability-aware microarchitectures are necessary to sustain performance as the probability of errors increases.

Investigators:
Margarida Jacome Dept. of Electrical and Computer Engineering, U.T. Austin (Principal Investigator)
Gustavo de Veciana Dept. of Electrical and Computer Engineering, U.T. Austin

Graduate Students:
Elias Mizan
Andrey Zykov

Support: This project is partially supported by NSF: Foundations of Computing Processes and Artifacts Cluster

Publications:
High-performance computing on fault-prone nanotechnologies: Novel microarchitecture techniques exploiting reliability-delay trade-offs. (Not available)
M. Jacome, E. Mizan, A. Subramanian, A. Zykov, and G. de Veciana,   In preparation.

Links

Center for nano- & molecular science and technology (CNM) for ongoing interdisciplinary U.T. based reserach in this area and pointers to activities elsewhere.