| Embedded Computing | Hw/Sw Codesign | Emerging Nanotechnologies, NanoComputing Systems |
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Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media
Processing. Anand Ramachandran and Margarida F. Jacome,
IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, to appear, 2004.
Predicated Switching - Optimizing Speculation on EPIC Machines.
Satish Pillai and Margarida F. Jacome,
IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, to appear, 2004.
Power Aware Embedded Computing.
Margarida F. Jacome and Anand Ramachandran,
In Information Technology Handbook, Editor Richard Zurawski, CRC
Press, FL, 1-20, To Appear in 2004. (Soft copy not available.)
Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem
for Embedded Media Processing.
Anand Ramachandran and Margarida F. Jacome,
In Proc. of IEEE/ACM Design Automation Conference (DAC),
pages 137-142, June 2003.
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines:
Predication, Speculation and Modulo Scheduling.
Satish Pillai and Margarida F. Jacome,
In Proc. of IEEE/ACM Design Automation and Test in
Europe (DATE), pages 422-427, March 2003.
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines.
Satish Pillai and Margarida F. Jacome, Chapter in Embedded Software
for SoC, Editor Ahmed A. Jerraya, Kluwer Academic Publishers, MA, 245-
259, 2003. (Soft copy not available.)
Exploring performance tradeoffs for clustered VLIW ASIPs.
M. Jacome, G. de Veciana, and V. Lapinskii.
In The Best of ICCAD - 20 Years of Excellence in Computer Aided Design
, pages 159-177, Kluwer Academic Publishers, 2003. (See ICCAD'2000 paper
with the same title & authors.)
RS-FDRA - A Register Sensitive Software Pipelining Algorithm for
Embedded VLIW Processors.
Cagdas Akturan and Margarida F. Jacome,
IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, Vol. 21, No. 12, 1395-1415, December 2002.
An Effective Software Pipelining Algorithm for Clustered Embedded
VLIW Processors.
Cagdas Akturan and Margarida F. Jacome,
Design Automation for Embedded Systems,
Vol. 7, No. 1, 115-138, September 2002.
Application-specific clustered VLIW datapaths: Early exploration on a
parameterized design space.
V. Lapinskii, M. Jacome, and G. de Veciana, IEEE Transactions on
Computer Aided Design,
Vol. 21, No. 8, 889-903, August 2002.
Cluster assignment for high-performance embedded VLIW processors.
V. Lapinskii, M. Jacome, and G. de Veciana, ACM Transactions on
Design Automation of Electronic Systems, Vol. 7, No. 3, 430-454, July
2002. Best Paper Award for the ACM Transactions on Design Automation of
Electronic Systems (TODAES) during the period Jan 2002 to Jan 2004.
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded
VLIW Processors.
Cagdas Akturan and Margarida F. Jacome,
In Proc. of IEEE/ACM International Conference on Computer Aided Design
(ICCAD), pages 112-118, November 2001.
High quality operation binding for clustered VLIW datapaths.
V. Lapinskii, M. Jacome, and G. de Veciana.
In Proc. IEEE/ACM Design Automation Conference (DAC), pages 702-707,
June 2001.
Clustered VLIW architectures with predicated switching.
M. Jacome, G. de Veciana, and S. Pillai.
In Proc. IEEE/ACM Design Automation Conference (DAC), pages 696-701,
June 2001.
RS-FDRA: A Register Sensitive Software Pipelining Algorithm for
Embedded VLIW Processors.
Cagdas Akturan and Margarida F. Jacome,
In Proc. of IEEE/ACM International Symposium on Hardware/Software
Codesign (CODES), pages 67-72, April 2001.
Lower bound on latency for VLIW ASIP datapaths.
M. Jacome and G. de Veciana,
In G. de Micheli, R. Ernst, and W. Wolf, editors,
Readings in Hardware /Software co-design ,
The Morgan Kaufmann series in Systems on Silicon,
Chapter 5, pages 477-484. Morgan Kaufman, 2001. (See ICCAD'1999 paper with the
same title & authors.)
Exploring performance tradeoffs for clustered VLIW ASIPs.
M. Jacome, G. de Veciana, and V. Lapinskii,
In Proc. of ACM/IEEE International Conference on Computer Aided Design
(ICCAD), pages 504-510, November 2000.
Received the IEEE/CAS William J. McCalla ICCAD Best Paper Award.
Symbolic Binding for VLIW ASIPs.
Satish Pillai and Margarida F. Jacome,
In Proc. of IEEE/ACM International Conference on Computer
Design (ICCD), pages 437-444, September 2000.
Design challenges for new application specific processors.
M. Jacome and G. de Veciana,
IEEE Design & Test of Computers, Vol. 12, No. 2, 40-50, April-June
2000.
Heuristic tradeoffs between latency and energy consumption in register
assignment.
R. Anand, M. Jacome, and G. de Veciana,
In Proc. of IEEE/ACM 8th International Workshop on Hardware/Software
Codesign (CODES),
pages 115-119, May 2000.
FDRA: A Software Pipelining Algorithm for Embedded VLIW
Processors. Cagdas Akturan and Margarida F. Jacome,
In Proc. of IEEE/ACM International Symposium on System
Synthesis (ISSS),
pages 34-40, September 2000.
Lower bound on latency for VLIW ASIP datapaths.
M. Jacome and G. de Veciana.
In Proc. of ACM/IEEE International Conference on Computer Aided Design
(ICCAD), pages 261-269, November 1999.
Resource constrained dataflow retiming heuristics for VLIW ASIPs.
M. Jacome, G. de Veciana, and C. Akturan.
In 7th International Workshop on Hardware/Software Codesign (CODES),
pages 12-16, May 1999.
Designing Dynamically Reconfigurable Systems: A High Level Approach.
Pedro Merino, Juan Carlos Lopez, and Margarida Jacome,
In Proc. of Proceedings of Design of Circuits and Integrated Systems
Conference (DCIS), pages 458-463, November 1998. (Soft copy not
available.)
Software Power Estimation and Optimization for High-Performance, 32-bit
Embedded Processors.
Jeffry Russell and Margarida F. Jacome,
In Proc. of Proceedings of IEEE International Conference on Computer
Design (ICCD),
pages 328-333, October 1998.
A Hardware Operating System for Dynamic Reconfiguration of FPGAs.
Pedro Merino, Juan Carlos Lopez, and Margarida Jacome,
In Proc. of International Workshop on Field Programmable Gate Arrays
(FPL), Lecture Notes in Computer Sciences, Springer, pages 431-435,
September 1998. (Soft copy not available.)
A Methodology for Task Based Partitioning and
Scheduling of Reconfigurable Systems.
Pedro Merino, Margarida Jacome, and Juan Carlos Lopez,
In Proc. of IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM),
pages 324-325, April 1998. (Soft copy not available.)
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Architectural probing: a new paradigm for enabling
communication refinement in SOC design.
Chen He, Marcello Lajollo and Margarida Jacome,
IEE Proceedings - Computers and Digital Techniques, Vol. 151, No. 1,
23-32, January 2004.
Performance Evaluation of Component Based
Embedded Systems.
Jeffry T. Russell and Margarida F. Jacome,
In Proc. of IEEE/ACM Design Automation Conference (DAC),
pages 396-401, June 2003.
A Case Study of a System Level Approach to Exploration of Queuing Management
Schemes for Input Queue Packet Switches. Chen He, Marcello Lajolo, and
Margarida Jacome. In Proc. 11th Euromicro Conference on Parallel
Distributed and Network Based Processing (PDP'03) , pages 401-408, Feb.
2003.
Scenario-Based Software Characterization as a Contingency to
Traditional Program Profiling.
Jeffry T. Russell and Margarida F. Jacome,
In Proc. of IEEE International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems (CASES),
pages 170-177, October 2002.
System-level Exploration of Queuing Management Schemes for Input Queue Packet
Switches. Chen He, Marcello Lajolo, and Margarida Jacome. In
Proc. International Workshop on IP-Based SOC Design , pages 233-238,
Oct. 2002.
A Survey of Digital Design Reuse.
Margarida F. Jacome and Helvio P. Peixoto,
IEEE Design and Test of Computers,
Vol. 18, No. 3, 98-107, May-June 2001.
The Common Hardware and Software Model: CHSOM.
Hugo A. Andrade and Margarida F. Jacome, In Proc. of International
Workshop of Engineering of Reconfigurable Hardware/Software Objects
(ENREGLE), June 2000. (Soft copy not available.)
A New technique for Estimating Lower Bounds on Latency for High Level
Synthesis. Helvio P. Peixoto, and Margarida F. Jacome,
In Proc. of ACM Great Lakes Symposium (GLSVLSI),
pages 129-132, March 2000.
Assessing probabilistic timing constraints on system performance.
G. de Veciana, M. Jacome, and J.-H. Guo,
Design Automation for Embedded Systems, Vol. 5, No. 1, 61-81,
February 2000.
A Tight Area Lower Bound for Sliced Floorplans.
Helvio P. Peixoto, Margarida Jacome and Ander Royo,
In Proc. of International Conference on VLSI Design,
January 2000.
Design Space Layer: Supporting Early
Design Space Exploration for Core Based Designs.
Helvio P. Peixoto, Margarida F. Jacome, Ander Royo, Juan C. Lopez,
In Proc. of ACM/IEEE Design, Automation and Test
in Europe (DATE), pages 676-683, March 1999. (Soft copy not available.)
Hierarchical Algorithms for Assessing Probabilistic Constraints on System
Performance. Gustavo de Veciana, Margarida F. Jacome, and J.-H. Guo,
In Proc. of IEEE/ACM Design Automation Conference (DAC),
pages 251-256, June 1998.
Embedded LabVIEW: A Case Study on the
Design of a Dedicated Execution Engine Tuned for Determinism and Real-Time
Performance.
Deepika Arora, Serban Catrava, Sam De Key, Margarida Jacome,
In Proc. of IEEE Conference on Computational Engineering in Systems
Applications, Vol. 1, pages 1207-1211, April 1998. (Soft copy not
available.)
Supporting Early System-Level Design Space Exploration in the
Deep-Submicron Era.
Margarida F. Jacome and Juan Carlos Lopez.
In Advanced Techniques for Embedded Systems Design and Test, Chapter
2, pages 31-52, Kluwer Academic Publishers, 1998. (Soft copy not available.)
Algorithm and Architecture-level Design Space Exploration Using
Hierarchical Data Flows.
Helvio P. Peixoto and Margarida F. Jacome,
In Proc. of International Conference on Application-specific Systems,
Architectures and Processors (ASAP),
pages 272-282, July 1997. (Soft copy not available.)
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Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics.
C. He and M. Jacome. IEEE Transactions on Computer Aided Design,
accepted for publication, August 2006.
RAS-NANO: A Reliability-Aware Synthesis Framework for Reconfigurable
Nanofabrics. C. He and M. Jacome.
In Proc. of IEEE/ACM Design Automation and Test in
Europe (DATE), March 2006.
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies.
C. He, M. Jacome, and G. de Veciana.
In IEEE Design & Test of Computers, Special Issue on
Advanced Technologies and Reliable Design for Nanotechnology Systems ,
July-August 2005.
Scalable Defect Mapping and Configuration of Memory-Based Nanofabrics.
C. He, M. Jacome, and G. de Veciana. In IEEE International High-
Level Design, Validation and Test Workshop (HLDVT) , Nov-Dec 2005.
High Performance Computing on Fault-Prone Nanotechnologies:
Novel Microarchitecture Techniques Exploiting Reliability-Delay Trade-offs.
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana,
Ajay Subramanian.
In Proc. IEEE/ACM Design Automation Conference (DAC) , 2005.
High Performance Computing on Fault-Prone Nanotechnologies:
Novel Microarchitecture Techniques Exploiting Reliability-Delay Trade-offs.
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana,
Ajay Subramanian. Technical Report CERC-TR-MJ-0502 , 2005.
Defect tolerant probabilistic design paradigm for nanotechnologies.
M. Jacome, C. He, G. de Veciana, and S. Bijansky.
In Proc. IEEE/ACM Design Automation Conference (DAC) , 2004.